1. Technical Field
The disclosed embodiments relate to CML logic buffers and to the communication of signals from CML logic buffers to loads.
2. Background Information
Digital logic circuitry is being used in applications involving signals of ever increasing frequencies. Within a cellular telephone, for example, digital circuitry is now used to realize high speed frequency dividers. The receiver chain of a cellular telephone, for example, may include a local oscillator having a phase locked loop. The frequency divider in the feedback loop of the phase-locked loop may be a digital counter. Parts of this counter, for speed reasons, may be realized in a type of logic referred to as “current mode logic” (CML). One type of CML logic gate is a buffer (sometimes called a “clock driver”).
FIG. 1 (Prior Art) is a diagram of a conventional non-inverting CML buffer 1 that is AC-coupled in conventional manner to a load 2. The load has two differential signal input nodes 3 and 4 for receiving differential signals. N-channel field effect transistors (FETs) 5 and 6 and resistors 7 and 8 represent circuitry that is typical of a CML load. The gate of transistor 5 is coupled to the load's differential signal input node 3. The gate of transistor 6 is coupled to the load's differential signal input node 4. Load 2 works properly when a DC bias voltage of an appropriate magnitude is present on the gates of transistors 5 and 6. The differential signals that are received on input nodes 3 and 4 transition above and below this DC bias voltage. Resistors 9 and 10 represent a biasing network that places an appropriate DC voltage VBIAS2 on the gates of transistors 5 and 6.
Buffer 1 receives differential CML input signals on a pair of differential signal input nodes 11 and 12 and drives differential CML output signals out of a pair of differential signal output nodes 13 and 14 to load 2. Buffer 1 typically involves an N-channel FET pulldown current source structure 15 that serves as the load for a pair of input N-channel pullup FETs 16 and 17. Current mirror structure 15 operates to sink DC bias currents 18 and 19 from output nodes 13 and 14, respectively. A remotely located bias voltage generator typically supplies a bias voltage VBIAS1 that determines the magnitudes of DC bias currents 18 and 19. When the received differential CML input signals are received onto differential signal input nodes 11 and 12, the transistors 16 and 17 are to communicate the differential signals onto differential signal output nodes 13 and 14. Each of the differential signal input signals varies over a voltage range and typically has a DC bias voltage offset. The DC bias voltages of the differential CML input signals in combination with the source-follower operation of transistors 16 and 17 and DC bias currents 18 and 19 serve to establish a DC bias voltage on differential signal output nodes 13 and 14. This DC bias voltage on the differential signal output nodes of buffer 1 is generally different than the DC bias voltages VBIAS2 that should be present on the gates of transistors 5 and 6 of load 2. The differential signal output nodes 13 and 14 of buffer 1 are therefore AC-coupled through capacitors 20 and 21 to the differential signal input nodes 3 and 4 of load 2. This allows the DC bias voltages of the buffer and load to be different, but allows transitioning differential signals to pass from buffer 1 to load 2.
FIG. 2 (Prior Art) is a waveform diagram that illustrates operation of conventional buffer 1 of FIG. 1. The upper waveform shows how a relatively high frequency signal having a pulse width of five hundred picoseconds passes through capacitors 20 and 21 from the buffer to the load. A lower frequency signal, however, is rejected due to the AC-coupling. The lower the frequency of the signal, the more the signal is rejected. The lower waveform shows how a relatively low frequency signal having a pulse width of ten microseconds is largely rejected by the AC coupling between buffer and load. By the end of the ten microsecond pulse of a digital logic value “high”, the voltage level of the signal has nearly fallen to a voltage defined to be the opposite digital logic value (a digital logic value “low”). By the end of the ten microsecond pulse, ninety percent of the signal has been attenuated. Accordingly, a typical CML buffer that is AC-coupled to its load may be employed only where the signals to be communicated to the load are of an adequately high frequency such that the desired signals make it to the load with adequate signal strength. A more versatile buffer circuit is desired.